1. Field of the Invention
The present invention relates to a transconductance compensating bias circuit and an amplifier.
2. Description of the Related Art
FIG. 1 is a diagram showing an amplifier circuit. The amplifier circuit includes a load resistor 101 and a field-effect transistor (FET) 103 connected in series between a high potential source and a low potential source. The drain of the FET 103 is connected to the output of the amplifier circuit. The source of the FET 103 is connected to the low potential source. The gate of the FET 103 is connected to a signal source S through a capacitor C. Further, the gate of the FET 103 is biased by a transconductance compensating bias circuit 105.
A change ΔIamp in the current flowing through the FET 103 is proportional to a change in the gate voltage Vin in a small signal region as follows:ΔIamp=Gm×ΔVin,   (1)where Gm is a constant of proportionality and is referred to as “transconductance.”
Accordingly, a change ΔVout in the voltage applied to the load resistor 101 is given by:ΔVout=R×ΔIamp=R×Gm×ΔVin,   (2)where R is the resistance of the load resistor 101. The gain of the amplifier is defined by R×Gm.
This type of amplifier circuit is biased by the transconductance compensating bias circuit 105 so as to cause the gain R×Gm to be a constant value. The transconductance compensating bias circuit 105 suitably biases the gate of the FET 103 so as to ensure that the transconductance Gm of the FET 103 is inversely proportional to the resistance R of the load resistor 101. By causing the gain R×Gm to be a constant value, it is possible to reduce a variation in the amplification characteristic originating from the manufacturing process of the FET 103 or due to a change in temperature at the time of operation. This is because in general, resistors of the same type change in the same manner in response to a change in the manufacturing process in an integrated circuit such as LSI.
FIG. 2 is a diagram showing a circuit used in the transconductance compensating bias circuit 105 of FIG. 1. The transconductance compensating bias circuit 105 includes first and second p-channel FETs 201 and 203 and first and second n-channel FETs 205 and 207. The first p-channel FET 201 has a source connected to a high potential source (for example, a 3 V constant potential source Vdd), a gate, and a drain connected to the gate. The first n-channel FET 205 has a drain connected to the drain of the first p-channel FET 201, a gate, and a source connected to a low potential source through a resistor Rs. The second p-channel FET 203 has a source connected to the high potential source, a gate connected to the gate of the first p-channel FET 201, and a drain. The second n-channel FET 207 has a drain connected to the drain of the second p-channel FET 203, a gate connected to the drain, and a source connected to the low potential source.
In general, the transconductance compensating bias circuit 105 forms a current mirror circuit, so that a reference current Iref flowing through the first p-channel FET 201 and the first n-channel FET 205 is reflected in a bias current Iout flowing through the second p-channel transistor 203 and the second n-channel transistor 207. In FIG. 2, W and L indicate the width and length, respectively, of the gate of the FET, and K represents the scale factor of the FET. In this case, if the reference current Iref and the bias current Iout are equal, the transconductance gm of the second n-channel FET 207 can usually be approximated as follows:
                              gm          =                                                    2                Rs                            ⁢                              (                                  1                  -                                      1                                          K                                                                      )                                      ∝                          1              Rs                                      ,                            (        3        )            where Rs represents the resistance of the resistor Rs connected to the source of the first n-channel FET 205.
As shown in the above-described formula (3), the transconductance gm of the second n-channel FET 207 is inversely proportional to the resistance of the resistor Rs if Iref=Iout. Accordingly, it is possible to stabilize the gain of the amplifier circuit by causing a current proportional to Iref (Iout) to flow through the amplifier circuit (for example, Iamp of FIG. 1). The technique of using gm being proportional to 1/Rs in the case of Iref=Iout is described in, for example, Razavi, B.; Design of Analog CMOS Integrated Circuit, p. 379.
FIG. 3 is a graph showing the relationship between drain current and drain voltage with respect to the first and second n-channel FETs 205 and 207 of FIG. 2. If the resistance RDS between the source and drain of an FET is relatively large, the drain current hardly changes even if the drain voltage changes to some extent. Accordingly, even if there is some difference between the drain voltages V1 and V2 of the first and second n-channel FETs, respectively, the relationship of Iref=Iout is maintained, and the above-described approximation of gm∝1/Rs holds, so that the above-described intended operation is ensured.
As the source-drain resistance RDS has become relatively small with progress in the miniaturization of transistors, a change in the drain current in response to a change in the drain voltage cannot be ignored. Therefore, the drain voltages V1 and V2 of the first and second n-channel FETs 205 and 207, respectively, are required to be equal, for otherwise, Iref and Iout are not equal (Iref≠Iout) because of the voltage difference.
Further, there may be a change in the potential difference between the drain voltages V1 and V2 of the first and second n-channel FETs 205 and 207, respectively, because of a change in the manufacturing process or operating temperature. In this case, the difference between Iref and Iout also changes, so that the ratio of gm to 1/Rs also changes. As a result, the above-described intended operation is not ensured.